The present invention relates to integrated circuits and more particularly, the present invention relates to a recovery method for a NAND flash memory device.
A NAND flash memory device comprises a plurality of cell blocks. Each of the cell blocks includes a plurality of cell strings. A plurality of cells for storing data are connected in series to form a string. A drain select transistor is formed between the cell strings and a drain and a source select transistor is formed between the cell string and a source.
In a conventional cell of a NAND flash memory device, an isolation region is provided in a semiconductor substrate. The isolation region can be formed using for example, a Shallow Trench Isolation (STI) process. A gate structure is formed in a region of the semiconductor substrata. The gate structure comprises a tunnel oxide layer, a floating gate, a dielectric layer, and a control gate. A junction is formed on each sides of the gate structure.
Certain limitations exist with the conventional NAND flash memory device. As the design rule is reduced, distance between cells is reduced. The state of a cell may be influenced by the state of a neighboring cells. For example, a threshold voltage of a program cell can be influenced by a threshold voltage of peripheral cells during a programming operation. When the peripheral cells are excessively erased, the threshold voltage of the program cell is changed accordingly. Therefore, the distribution characteristic of the threshold voltage of the program cell is changed leading to chip failure. These and other limitations will be described in more detail throughout the present specification.